1. Field of the Invention
The present invention relates generally to a circuit for testing array packages, and more particularly, to a circuit for more readily detecting failures of solder joints on array packages.
2. Description of Related Art
Large array packages used for implementing integrated circuits or programmable logic devices, such as field programmable gate arrays (FPGAs), are commonly employed in digital electronics and electronic systems. Often, these array packages are electrically and mechanically coupled to, for example, circuit boards or circuit cards and other associated components, through various solder joint connections associated with, for example, a ball grid array.
The solder joint connections between the array package and the circuit board can fail over time due to mechanical fatigue. Such mechanical fatigue can be caused, for example, by repeated vibration of the electronic system during operation, or by repeated thermal cycles when the array package has a different coefficient of thermal expansion and/or changes temperatures faster or slower than the circuit board during operation. When one or more of the solder joints fails, the system may not be able to function properly.
Previous testing procedures for detecting failed or failing solder joints have been used, but are too costly, overly complex to implement, or both. In addition, some testing procedures identify failures only when a complete disconnect occurs. Some other testing procedures require the operation of the array package or the circuit to be interrupted or stopped.